The present invention relates to a method for fabricating a semiconductor memory device, more particularly relates to a method for fabricating a semiconductor memory device, in which a tunnel insulating layer is protected from exposure to an etching process for a gate pattern to prevent etching damage to the tunnel insulating layer.
In a semiconductor flash memory device, a gate pattern is generally formed by patterning a conductive layer for a floating gate, a dielectric layer, a conductive layer for a control gate and a gate electrode layer.
FIG. 1 is a sectional view of a semiconductor memory device illustrating a method for manufacturing a semiconductor device according to a conventional technique.
Referring to FIG. 1, a tunnel insulating layer 11, a conductive layer 12 for a floating gate, a dielectric layer 13, a conductive layer 14 for a control gate and a gate electrode layer 15 are sequentially formed on a semiconductor substrate 10. Then, a hard mask pattern is formed, and an etching process using the hard mask pattern is performed to pattern the gate electrode layer 15. Subsequently, the conductive layer 14 for a control gate, the dielectric layer 13 and the conductive layer 12 for a floating gate are sequentially etched to expose the tunnel insulating layer 11.
In the above process for forming the gate patterns in a semiconductor memory device according to the conventional technology, the etching process is performed until the tunnel insulating layer is exposed. Then, a cleaning process is performed to remove polymer generated in the etching process.
The tunnel insulating layer may be damaged by overetching during the etching process or by the cleaning process, degrading a characteristic of the tunnel insulating layer. Due to the above phenomenon, a charge loss may be caused after a program operation of the memory device is completed, thereby degrading a data retention characteristic of the device.